Implementing auto-configurable default polarity

ABSTRACT

The present invention relates to a system and method for implementing auto-configurable default polarity. More specifically, the present invention relates to a transceiver module comprising, for example, a single chip multi-sublayer PHY, where the single chip multi-sublayer PHY is adapted to implement auto-configurable default polarity. In one embodiment, the transceiver module comprises at least one program module adapted to be programmed with at least a default polarity setting. The single-chip multi-sublayer PHY comprises at least one selection register communicating with at least the program module, where the selection register is adapted to store at least the default polarity setting. The single chip multi-sublayer PHY further comprises at least one multiplexer communicating with at least the selection register and adapted to select one polarity from at least two possible polarities based at least in part on the default polarity setting.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application is related to, and is a continuation of, U.S.application Ser. No. 10/372,158, dated Feb. 21, 2003, which claimsbenefit of and priority from U.S. Provisional Application No. 06/402,096dated Aug. 7, 2002, titled “System and Method For ImplementingAuto-Configurable Default Polarity”, the complete subject matter ofwhich is incorporated herein by reference in its entirety.

U.S. Pat. No. 6,424,194, U.S. application Ser. No. 09/540,243 filed onMar. 31, 2000, U.S. Pat. No. 6,389,092, U.S. Pat. No. 6,340,899, U.S.application Ser. No. 09/919,636 filed on Jul. 31, 2001, U.S. applicationSer. No. 09/860,284 filed on May 18, 2001, U.S. application Ser. No.10/028,806 filed on Oct. 25, 2001, U.S. application Ser. No. 09/969,837filed on Oct. 1, 2001, U.S. application Ser. No. 10/159,788 entitled“Phase Adjustment in High Speed CDR Using Current DAC” filed on May 30,2002, U.S. application Ser. No. 10/179,735 entitled “UniversalSingle-Ended Parallel Bus; fka, Using 1.8V Power Supply in 0.13MM CMOS”filed on Jun. 21, 2002, and U.S. Application Ser. No. 60/402,097entitled “System And Method For Implementing A Single Chip Having AMultiple Sub-Layer Phy” filed on Aug. 7, 2002 (Attorney Docket No.1772-13906US01) and U.S. application Ser. No. 10/282,933 entitled“System And Method For Implementing A Single Chip Having A MultipleSub-Layer Phy” filed on Oct. 29, 2002 (Attorney Docket No.1772-13906U502) are each incorporated herein by reference in theirentirety.

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BACKGROUND OF THE INVENTION

Embodiments of the present invention relate generally to a method andsystem for implementing polarity for a single chip.

High-speed digital communication networks over copper and optical fiberare used in many network communication and digital storage applications.Ethernet and Fiber Channels are two widely used communication protocolsthat continue to evolve in response to the increasing need for higherbandwidth in digital communication systems.

The Open Systems Interconnection (alternatively referred to as the“OSI”) model (ISO standard) was developed to establish standardizationfor linking heterogeneous computer and communication systems. The OSImodel includes seven distinct functional layers including Layer 7: anapplication layer; Layer 6: a presentation layer; Layer 5: a sessionlayer; Layer 4: a transport layer; Layer 3: a network layer; Layer 2: adata link layer; and Layer 1: a physical layer. Each OSI layer isresponsible for establishing what is to be done at that layer of thenetwork but not how to implement it.

Layers 1 to 4 handle network control, and data transmission andreception. Layers 5 to 7 handle application issues. It is contemplatedthat specific functions of each layer may vary to a certain extent,depending on the exact requirements of a given protocol to beimplemented for that layer. For example, the Ethernet protocol providescollision detection and carrier sensing in the physical layer.

The physical layer (i.e., Layer 1) is responsible for handling allelectrical, optical, and mechanical requirements for interfacing to thecommunication media. The physical layer provides encoding and decoding,synchronization, clock data recovery, and transmission and reception ofbit streams. Typically, high-speed electrical or optical transceiversare the hardware elements used to implement such layer.

As data rate and bandwidth requirements increase, 10 Gigabit datatransmission rates are being developed and implemented in high-speednetworks. Pressure exists to develop a 10 Gigabit physical layer forhigh-speed serial applications. Transceivers for 10 G applications areneeded for the 10 G physical layer. The specification IEEE P802.3aedraft 5 describes the physical layer requirements for 10 Gigabitapplications and is incorporated herein by reference in its entirety.

An optical-based transceiver, for example, includes various functionalcomponents such as clock data recovery, clock multiplication,serialization/de-serialization, encoding/decoding, electrical/opticalconversion, descrambling, media access control, controlling, and datastorage. Many of the functional components are often implemented inseparate IC chips.

It is currently known that transceivers may have a different polarityfrom the devices or upper level systems with which they are associated(alternatively referred to as “associated devices”). Such differentpolarities must be accommodated. Some solutions have included insertingone or more chips between the transceiver and the associated devices (orsoftware) to re-configure the polarity. It is contemplated thatinserting such a chip may affect production cost and time. Furthermore,such chips may not work correctly, adversely affecting the communicationbetween the transceiver and the associated devices.

Another solution involves making at least two versions of thetransceiver, a first version having one polarity, and a second versionhaving the opposite polarity. It is contemplated that this solution issusceptible to error, in that the wrong version of the transceiver maybe used, adversely affecting communication between the transceiver andthe associated devices.

A further solution involves the crossing of signal paths to achievecorrect polarity. This solution, however, results in signal degradation.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Aspects of the present invention address one or more of the problemsoutlined above. One embodiment of the present invention relates to asystem and method for implementing auto-configurable default polarity.

One embodiment relates to a single chip multi-sublayer PHY system. Inthis embodiment, the single chip multi-sublayer PHY comprises at leastone selection register adapted to store at least one default polaritysetting and at least one selection module communicating with at leastthe selection register and adapted to select one polarity from at leasttwo possible polarities based at least in part on the default polaritysetting.

In another embodiment, the selection module of the single chipmulti-sublayer PHY comprises at least one multiplexer. This embodimentmay further comprise an inverter coupled to at least the selectionmodule. At least one differential driver may be coupled to the selectiondevice having at least one output interface coupled thereto. Thisembodiment may further comprise a polarity override interfacecommunicating with the selection register and adapted to communicate anoverride signal thereto. Additionally, the embodiment may comprise atleast one program module or EEPROM coupled to the selection register.

Another embodiment of the present invention comprises a transceiver. Inthis embodiment the transceiver comprises at least one program moduleadapted to be programmed with at least a default polarity setting and asingle chip multi-sublayer PHY. Further, the single chip multi-sublayerPHY comprises at least one selection register communicating with atleast the program module and at least one selection module communicatingwith at least the selection register. In this embodiment, the selectionregister is adapted to store at least the default polarity setting,while the selection module is adapted to select one polarity from atleast two possible polarities based at least in part on the defaultpolarity setting.

Yet another embodiment of the present invention relates to a method ofconfiguring a polarity for a transceiver module. The embodimentcomprises writing a default polarity into at least one programmingmodule, writing or storing the default polarity into at least oneselection register on a single chip multi-sublayer PHY and selecting thepolarity from at least two possible polarities using at least thedefault polarity. This embodiment may also comprise overriding thedefault polarity and selecting the polarity from at least two possiblepolarities using at least the overridden default polarity

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a transceiver system in accordancewith one embodiment of the present invention.

FIG. 2 illustrates a block diagram of a single chip multi-sublayer PHYdevice in accordance with one embodiment of the present invention.

FIG. 3 illustrates a block diagram of a single chip multi-sublayer PHYdevice similar to that of FIG. 2 including a selection register andmultiplexer in accordance with one embodiment of the present invention.

FIG. 4 illustrates a high level flow diagram of a method forauto-configuring a polarity using, for example, a single chipmulti-sublayer PHY in accordance with one embodiment of the presentinvention.

FIG. 5 illustrates a detailed flow diagram of a method forauto-configuring a polarity using, for example, a single chipmulti-sublayer PHY in accordance with one embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a schematic block diagram illustrating certaincomponents of a Gigabit transceiver module, generally designated 5, witha XAUI interface 15 in accordance with an embodiment of the presentinvention. The transceiver module 5 may, in one embodiment of thepresent invention, be compatible with the XENPAK optical modulestandard. The transceiver module 5 includes, for example, a single-chipmulti-sublayer PHY 10, an optical PMD 30, and an EEPROM 40.

According to an embodiment of the present invention, a media accesscontroller (alternatively referred to as “MAC”) 20 interfaces to thesingle-chip multi-sublayer PHY 10 through the XAUI transmit and receiveinterface 15. In general, the MAC layer comprises one of two sublayersof the data link control layer and is concerned with sharing thephysical connection to a network among several upper-level systems. Inthis embodiment, the single-chip multi-sublayer PHY 10 interfaces to theoptical PMD 30 through a PMD transmit and receive interface 17. The MAC20 also interfaces to the single-chip multi-sublayer PHY 10 through theserial management data input/output (alternatively referred to as an“MDIO”) interface 16. The single-chip multi-sublayer PHY 10 alsointerfaces to EEPROM 40 through a two-wire serial interface 19. In thisembodiment, a XGMII interface is not used.

The XAUI interface 15 comprises 4 channels of 3 Gigabit serial datareceived by the single-chip multi-sublayer PHY 10 from the MAC 20 and 4channels of 3 Gigabit serial data transmitted from the single-chipmulti-sublayer PHY 10 to the MAC 20. In an embodiment of the presentinvention, the MAC 20 includes a XGXS sublayer interface 21 and areconciliation sublayer or RS interface 22. In one embodiment of thepresent invention, for Ethernet operation for example, the 3 Gigabitdata rate is actually 3.125 Gbps and for Fibre Channel operation forexample, the 3 Gigabit data rate is actually 3.1875 Gbps.

The PMD interface 17 comprises a 10 Gigabit serial transmit differentialinterface and a 10 Gigabit serial receive differential interface betweenthe single-chip multi-sublayer PHY 10 and the optical PMD 30 inaccordance with an embodiment of the present invention. In oneembodiment of the present invention, for Ethernet operation for example,the 10 Gigabit data rate is actually 10.3125 Gbps and for Fibre Channeloperation for example, the 10 Gigabit data rate is actually 10.516 Gbps.

FIG. 2 illustrates a schematic block diagram of the single-chipmulti-sublayer PHY 10 used in the transceiver module 5 of FIG. 1 inaccordance with an embodiment of the present invention. The single-chipmulti-sublayer PHY 10 comprises a PMD transmit (alternatively referredto as “TX”) module 110, a PMD receive (alternatively referred to as“RX”) module 120, a digital core module 130, a XAUI transmit or TXsection 140, and a XAUI receive or RX module 150.

One exemplary embodiment of the present invention relates to a systemand method for implementing auto-configurable default polarity. In thisembodiment, a transceiver module (similar to those provided above, forexample) includes a single chip multi-sublayer PHY adapted to implementauto-configurable default polarity.

FIG. 3 illustrates one embodiment of the present invention comprising atleast one program module adapted to be programmed with at least adefault polarity setting. More specifically, the program module maycomprise an EEPROM 160 that is adapted to be programmed with one or moredefault polarity settings. While an EEPROM is discussed, other programmodules are contemplated. Moreover, it is contemplated that the EEPROMmay be on the single chip multi-sublayer PHY or otherwise on thetransceiver module, or outside the transceiver module but in the upperlevel system. It may be desirable to program the EEPROM in a giventransceiver module such that the programmed polarity is compatible withthe particular customer that will use the given transceiver module.

In the illustrated embodiment, the program module communicates with atleast one selection register 170, where the selection register isadapted to store at least the default polarity setting. In thisembodiment, the default polarity setting is programmed or written intothe EEPROM 160. Upon start-up, such default polarity setting iscommunicated to the selection register 170.

One embodiment of the single chip multi-sublayer PHY further comprisesat least one selection module or device 180 (for example, a multiplexeror mux) communicating with at least the selection register 170 andadapted to select at least one polarity from at least two possiblepolarities based at least in part on the default polarity setting. Inthis embodiment, at least two signals 191 and 192 having differentpolarities (for example a first signal having a first polarity and asecond signal having a second polarity) are communicated to the mux 180.As an example, if the default polarity corresponds to the polaritydetermined at the output by signal 191, then signal 191 is selected bythe mux 180. Alternatively, if the default polarity corresponds to thepolarity determined at the output by signal 192, then signal 192 isselected by the mux 180.

In this embodiment, an inverter 193 is shown coupled to the mux 180,such that the second polarity is the inverse or opposite of the firstpolarity, although other relationships between the two signals and theirrespective polarities is contemplated. Further a differential driver 195is illustrated communicating with the mux 180 and an output interface196 (a differential twisted pair for example).

It is contemplated that, in one embodiment, it may be desirable tochange the default polarity setting stored in the selection register.FIG. 3 further illustrates a polarity override interface 197 coupled toand communicating with the selection register 170. In one embodiment,the polarity interface enables overriding of the default polaritysetting stored in the selection register, such that a different polaritymay be used. It is also contemplated that, in one embodiment, adifferent polarity setting may be programmed into the program module orEEPROM 160 and communicated to the selection register 170.

FIG. 4 illustrates a high level flow diagram illustrating one embodimentof the present invention relating to a method, generally designated 200,for auto-configuring a polarity (for a transceiver module for example)using a single chip multi-sublayer PHY, for example. This embodimentcomprises programming a default polarity using at least one programmingmodule and writing the default polarity into at least one selectionregister on the single chip multi-sublayer PHY as illustrated by blocks210 and 212 respectively. The single chip multi-sublayer PHY selects thepolarity from at least two possible polarities using at least thedefault polarity as illustrated by block 214. For example, if at theoutput, the default polarity corresponds to the first signal (signal 191for example) the mux selects the first signal. If at the output, thedefault polarity corresponds to a second signal (signal 192 for example)the mux selects the second signal.

FIG. 5 illustrates a detailed flow diagram of a method, generallydesignated 300, for auto-configuring a polarity using, for example, asingle chip multi-sublayer PHY in accordance with one embodiment of thepresent invention. This embodiment comprises writing one or more defaultpolarity settings into the program module as illustrated by block 310.In one embodiment, the default polarity setting is programmed or writteninto the program module or EEPROM. Upon start-up, such default polaritysetting is communicated to at least one selection register asillustrated by block 312, where the selection register is adapted tostore at least the default polarity setting.

In the illustrated embodiment, method 300 determines whether the defaultpolarity settings are used by an associated device as illustrated bydiamond 314. In other words, for example, a user (e.g., a customerdesiring to couple the transceiver module of the present invention to anassociated device) determines whether the associated device has apolarity that corresponds to the default polarity. If the defaultpolarity settings are used by the associated device, the selectiondevice or module (e.g., the mux) communicating with at least theselection register, selects the polarity (corresponding to the defaultpolarity for example) from at least two possible polarities asillustrated by block 316. In this embodiment, the selection device ormodule selects the one polarity based at least in part on the defaultpolarity setting.

However, if the default polarity settings is used by the associateddevice, the default polarity is overridden such that a differentpolarity setting may be communicated and stored in the at least oneselection register as illustrated by block 320. In other words, forexample, the user may modify the default polarity so that it correspondsto the polarity of the associated device. In this embodiment, thepolarity override coupled to and communicating with the selectionregister is used to override the default setting. The selection deviceor module (e.g., the mux) communicating with at least the selectionregister, selects another polarity from the possible polarities asillustrated by block 322.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the invention without departing from its scope.Therefore, it is intended that the invention not be limited to theparticular embodiment disclosed, but that the invention will include allembodiments falling within the scope of the appended claims.

1. PHY system comprising: at least one selection register adapted tostore at least one default polarity setting; and at least one selectionmodule communicating with said at least one selection register andadapted to select at least one polarity from at least two possiblepolarities based at least in part on said default polarity setting. 2.The system of claim 1, wherein said selection module comprises at leastone multiplexer.
 3. The system of claim 1 comprising an inverter coupledto at least said selection module.
 4. The system of claim 1 comprising adifferential driver coupled to said selection module.
 5. The system ofclaim 4 comprising at least one output interface coupled to at leastsaid differential driver.
 6. The system of claim 1 comprising a polarityoverride interface communicating with said selection register andadapted to communicate an override signal thereto.
 7. The system ofclaim 1, further comprising at least one program module coupled to saidselection register.
 8. The system of claim 7, wherein said at least oneprogram module comprises an EEPROM.
 9. A transceiver comprising: atleast one program module adapted to be programmed with at least adefault polarity setting; and a PHY comprising: at least one selectionregister communicating with at least said program module, said selectionregister adapted to store at least said default polarity setting; and atleast one selection module communicating with said at least oneselection register and adapted to select at least one polarity from atleast two possible polarities based at least in part on said defaultpolarity setting.
 10. The transceiver of claim 9, comprising at leastone optical PMD communicating with said PHY.
 11. The transceiver ofclaim 10, comprising at least one PMD transmit and receive interfacecoupled to said optical PMD and said PHY.
 12. The transceiver of claim11, wherein said PMD transmit and receive interface comprises a 10Gigabit serial transmit differential interface and a 10 Gigabit serialreceive differential interface.
 13. The transceiver of claim 9, whereinsaid at least one selection module comprises a multiplexer.
 14. Thetransceiver of claim 9 comprising an inverter coupled to at least saidselection module.
 15. The transceiver of claim 9 comprising adifferential driver coupled to said selection module.
 16. Thetransceiver of claim 15 comprising at least one output interface coupledto at least said differential driver.
 17. The transceiver of claim 9comprising a polarity override interface communicating with saidselection register and adapted to communicate an override signalthereto.
 18. A method of configuring a polarity for a transceiver modulecomprising: writing a default polarity into at least one programmingmodule; storing said default polarity into at least one selectionregister on a PHY; and selecting a polarity from at least two possiblepolarities using at least said default polarity.
 19. The method of claim18 comprising overriding said default polarity.
 20. The method of claim19 comprising selecting the polarity from at least two possiblepolarities using at least said overridden default polarity.